1. Field of the Invention
The present invention generally relates to a novel diode structure for ESD protection and its application circuits. More specifically, the present invention relates a novel diode structure having a circular gate to isolate the p-n junction of the novel diode from STI regions.
2. Description of the Related Art
With scaled-down device dimensions, shallower junction depth, thinner gate oxide, LDD (light-doped drain) structure, and salicide process in advanced deep-submicron CMOS technologies, CMOS IC products have become more susceptible to ESD (electrostatic discharge)-caused damage. Therefore, the ESD protection circuit has been built on the chip to protect devices and circuits against ESD damage.
The traditional ESD protection circuit to protect an input (or output) pad is often formed by the diodes, as shown in FIG. 1a and FIG. 1b. A primary ESD protection circuit is formed by diodes Dp1 and Dn1. In FIG. 1a, the Dn1 diode is connected from the pad 10 to VSS, and the Dp1 is connected from the pad 10 to VDD. To provide a more effective clamp on the ESD overstress voltage, the additional diodes (Dp2 and Dn2), forming a secondary ESD protection circuit, are added in FIG. 1b. 
There are four different ESD-stress conditions on a pad with respect to the VDD or VSS pads. These four ESD stresses are:
(1) PS mode: When a positive ESD exerts stress on the pad with the VSS relatively grounded (the VDD is floating during such an ESD stress condition), the p-n junction of Dn1 diode is broken down by the overstress voltage on the pad to bypass the ESD current from pad 10 to VSS.
(2) NS mode: When a negative ESD exerts stress on the pad with the VSS relatively grounded (the VDD is floating during such an ESD stress condition), the p-n junction of Dn1 diode is forward biased by the overstress voltage on the pad to bypass the ESD current from VSS to pad 10.
(3) ND mode: When a negative ESD exerts stress on the pad with the VDD relatively grounded (the VSS is floating during such an ESD stress condition), the p-n junction of Dp1 diode is broken down by the overstress voltage on the pad 10 to bypass the ESD current from VDD to pad.
(4) PD mode: When a positive ESD exerts stress on the pad 10 with the VSS relatively grounded (the VDD is floating during such an ESD stress condition), the p-n junction of Dn1 diode is forward biased by the overstress voltage on the pad 10 to bypass the ESD current from pad 10 to VDD.
The power generated by the ESD on the diode can be calculated as: Power=IESDxc3x97Vop, Where the IESD is the ESD current passing through the diode and the Vop is the operating point of the diode under the ESD stress. When the diode is in the reverse-biased condition, it typically has a breakdown voltage higher than 10V. But, when the diode is forward biased to conduct current, the forward biased voltage may be as small as 1V. Because the diode in the PS-mode or ND-mode ESD stresses is reverse biased, the ESD pulse generates a much higher temperature on the diode junction to burn out the diode. The diode in the breakdown condition has a much lower ESD robustness, as compared to the forward-biased condition. Therefore, the design challenge, including the layout and device structure, is how to sustain a higher ESD stress in the reverse-biased condition.
A conventional structure for the P-type diodes, Dp1 and Dp2, being realized in the CMOS process with the STI isolation is shown in FIG. 2, wherein a p+ diffusion 16 (as the anode) is placed in an N-well 20 to form the p-n junction of the diode. The cathode of such a P-type diode is connected out by the N+ diffusion 26 in the N-well 20. In a 0.25 m CMOS process, the p+ or N+ diffusion has a junction depth of 0.2 m. Between the p+ and N+ diffusion, there is the shallow-trench-isolation (STI) field oxide 14 to isolate these two diffusions. On the contrary, the N-type diode, Dn1 or Dn2, realized in the CMOS process with the STI isolation is shown in FIG. 3, where a N+ diffusion 18 (as the cathode) is placed in a P-well 24 or P-substrate 40 to form the p-n junction of the diode. The anode of such N-type diode is connected out by the p+ diffusion 28 in the P-well (or substrate) 24. Between the p+ diffusion 28 and the N+ diffusion 18, there is the STI field-oxide 14 to isolate these two diffusions.
When such P-type or N-type diodes are stressed by the ESD voltage in the reverse-biased conditions, the diffusion boundary to the STI is easily damaged by the ESD and causes a very low ESD robustness. As Voldman had illustrated in the paper xe2x80x9cSemiconductor process and structure optimization of shallow trench isolation-defined and polysilicon-N-bound source/drain diodes for ESD networksxe2x80x9d of Proc. Of EOS/ESD Symp., 1998, pp. 151-160. The weakest point on the STI-boundary diode structure over the ESD stress is shown in FIG. 4, where the STI field-oxide region near the p+ diffusion 16 has a pulldown structure 25. When the p-n junction is reversely biased during ESD stress, the breakdown point is located at the boundary 23 between the p+ diffusion 16 and STI region 14. Due to the limited area of the boundary for heat dissipation, this pulldown structure 25 on the STI boundary causes the p+ diffusion 16 having a lower ESD robustness on its diffusion edge. If the CMOS process has the salicide 11, the salicide 11 covered on the p+ diffusion 11 causes a bend down corner 21 at the boundary between the d+ diffusion 16 and the STI region. This bend down corner 21 causes the diode to be more easily damaged by ESD from a large amount of current flowing toward the region 23. Thus, when the advanced CMOS process has the STI or salicide, the ESD protection circuit often has very low ESD robustness, even if the diodes have been drawn with a larger silicon area.
To overcome the weak ESD damage on the STI-boundary p-n junction, Veldman further proposes a modified P-type diode structure as shown in FIG. 5. As compared to FIG. 2, the poly gates replace the STI regions between the p+ diffusion 16 and the n+ diffusion 26. To form the N+ diffusion 26 and the p+ diffusion 16, the poly gates are therefore doped by both N+ and p+ implantation, as shown in FIG. 5. The poly gate close to the n+ diffusion 26 is doped with N+ implantation (as numerical 19), whereas the poly gate close to the p+ diffusion 16 is doped with p+ implantation (as numerical 17). By a similar method, the N-type diode structure can be realized as shown in FIG. 6. The poly gates block the formation of the STI regions between the p+ and n+ diffusion regions in FIG. 5 and FIG. 6 during the CMOS fabrication process flow. Therefore, there is no STI boundary on the p+ (N+) diffusion edge of the P-type (N-type) diode in FIG. 5 (FIG. 6). Without the STI boundary close to the diffusion edge of the p-n junction of the diodes, the pulldown and bend-down corners in FIG. 4 are removed from the modified diode structure. Therefore, such diodes in FIG. 5 and FIG. 6 can sustain much higher ESD stress, as compared to the traditional diodes structure in FIG. 2 and FIG. 3.
Therefore, an object of the present invention is to provide a diode structure that doesn""t suffer from the formation of the STI regions.
Another object of the present invention is to provide a circuit structure for speeding up the turn-on speed of the proposed diode.
The present invention achieves the above-indicated objects by providing a diode for ESD protection. The diode comprises a first semiconductor layer of a first conductivity type and a MOS transistor of a second conductivity type. The first semiconductor layer is used as a first electrode. The MOS transistor is formed on the first semiconductor layer and has a circular gate, a first source/drain diffusion of the second conductivity type and a second source/drain diffusion of the second conductivity type. The circular gate locates in insulation on the first semiconductor layer. The first source/drain diffusion is formed on the first semiconductor layer enclosed by the circular gate, intervening into the first semiconductor layer to form a p-n junction and used as a second electrode of the diode. The second source/drain diffusion encloses the circular gate. The circular gate is used to prevent STI structure from forming on the p-n junction. One of the first and second electrodes is a cathode of the diode and is coupled to a first pad. The other is the anode of the diode and is coupled to a second pad. During an ESD stress, the circular gate is properly biased to speed up the turn-on speed of the diode.
The circular gate can be coupled to an ESD detection circuit. In normal operation, the ESD detection circuit provides a first voltage to the circular gate of the MOS of the diode for turning off the MOS. During an ESD event, the ESD detection circuit provides a second voltage to the circular gate of the MOS of the diode for lowering the breakdown voltage of the diode, such that the turn-on speed of the diode is increased.
Another aspect of the present invention is to provide an ESD protection circuit for the application on an IC chip. The ESD protection circuit comprises a diode. The diode comprises a first semiconductor layer of a first conductivity type and a MOS transistor of a second conductivity type. The first semiconductor layer is used as a first electrode. The MOS transistor comprises a circular gate, a first source/drain diffusion of the second conductivity type and a second source/drain diffusion of the conductivity type. The circular gate is located in insulation on the first semiconductor layer. The first source/drain diffusion is formed on the first semiconductor layer enclosed by the circular gate, as a second electrode. The second source/drain diffusion is formed on the first semiconductor layer, enclosing the circular gate. One of the first electrode and the second electrode is the cathode of the diode, coupled to a first pad; the other is the anode of the diode, coupled to a second pad.
Another aspect of the present invention is to provide a whole-chip ESD protection system. The whole-chip ESD protection system comprises a plurality of high voltage power lines VDD1 . . . VDDN, a plurality of low voltage power lines VSS1 . . . VSSN, a VDD ESD bus, a VSS ESD bus, a primary ESD protection circuit PESDP, a plurality of high-voltage-rail ESD protection circuits HESDP1 . . . HESDPN and a plurality of low-voltage-rail ESD protection circuits LESDP1 . . . LESPDN. The primary ESD protection circuit PESDP is coupled between the VDD ESD bus and the VSS ESD bus. HESDP1 . . . HESDPN are respectively coupled between VDD1 . . . VDDN and the VDD ESD bus. LESDP1 . . . LESPDN are respectively coupled between VSS1 . . . VSSN and the VSS ESD bus. HESDPn comprises at least one diode coupled between VDDn and the VDD ESD bus. The diode comprises a first semiconductor layer of a first conductivity type as a first electrode of the diode and a MOS transistor of a second conductivity type. The MOS transistor comprises a circular gate, a first source/drain diffusion of the second conductivity type and a second source/drain diffusion of the second conductivity type. The circular gate is located in insulation on the first semiconductor layer and used as a second electrode. The first source/drain diffusion is formed on the first semiconductor layer enclosed by the circular gate and is used as a second electrode of the diode. The second source/drain diffusion is formed on the first semiconductor layer and enclosing the circular gate. When an ESD stress pulses between VDDn and VSSn, the diode is kept on to drain ESD current though HESDPn, PESDP and LESDPn, thereby release the ESD stress.
One of the advantages of the present invention is that the STI regions are isolated from the p-n junction of the diode by the circuit gate of the MOS. Therefore, the ESD robustness doesn""t suffer from the STI process.
Another advantage of the present invention is that, by properly biasing the circular gate of the MOS, the turn-on speed of the diode can be increased. As a result, the ESD sustaining level can be increased.